32kB RAM/ROM Technical

Electrical connections

The module plugs in to any one of the four paged ROM sockets on an unexpanded Model A/B. An 8kB,16kB or 32kB 28 pin ROM/EPROM can be plugged into the piggy back socket.

Two jumper wires connect with IC leg clips to write strobe (NWDS - IC73 pin 24) and the ROM selection enable (ROMSEL - IC26 pin 5).

Upto four boards can be installed in a Model A/B giving a total of 8 banks of sideways RAM and 8 banks of ROM.

Memory map

The BBC hardware maps the ROM sockets from left to right as ROM 12, 13, 14 & 15. The paged ROMs appear in the 64kB address space of the 6502 processor at addresses &8000 - &BFFF.

Each ROM/RAM board can select one of four banks. Two 16kB RAM banks and upto two 16kB ROM banks. So depending on which socket the module is installed in you will get the following paged ROM allocations.

From left to right:
IC52 : Banks 0=RAM, 4=RAM, 8=ROM, 12=ROM
IC58 : Banks 1=RAM, 5=RAM, 9=ROM, 13=ROM
IC100 : Banks 2=RAM, 6=RAM, 10=ROM, 14=ROM
IC100 : Banks 3=RAM, 7=RAM, 11=ROM, 15=ROM

RAM write protect

RAM write protect (WP) is software controlled so there are no physical write protect switches to mount. WP is handled by the Atmel programmable logic device on the boards. Commands are written to the paged ROM register at address &FE30. Each 16kB RAM bank has a separate write protect.

Set write protect command:
&2x - where x is the memory bank number in the BBC from 0-F hex

Clear write protect command:
&3x - where x is the memory bank number in the BBC from 0-F hex

Write protect can be easily set cleanly from BASIC with a short assembly snippet. Include this in your ROM load menu program.

Clean

The following BASIC program demonstrates how to set or clear write protect on a RAM bank cleanly from within a BASIC (or machine code) program.

10 P%=&C00
20 [.wpset:ORA #&20:STA &FE30:LDA &F4:STA &FE30:RTS:]
30 [.wpclr:ORA #&30:STA &FE30:LDA &F4:STA &FE30:RTS:]
40 INPUT A%
50 CALL wpset
60 INPUT A%
70 CALL wpclr

BASIC transfers A% to the A register on a CALL function.

The set subroutine takes the ROM number in A, bitwise ORs it with the write command &20 then writes that to the paged ROM register &FE30. This will also select that paged ROM. The operating system stores the currently selected ROM (in our case BASIC) in zero page location &F4 so load that into A then write it to the paged ROM register at &FE30. Return from subroutine and we are done.

Clear works the same but ORs with &30 the clear write protect command.

Quick and dirty

The write protect can be set or cleared directly from BASIC. This method is quick for manually typed operations but dirty because it switches ROM while BASIC is still executing - potentially causing the computer to crash! But... since you need to reset the machine to get the OS to rescan the ROMs after loading a ROM image it works as a quick and dirty method.

Set WP:
?&FE30 = &2x
Clear WP:
?&FE30 = &3x

Where x is the RAM bank number.

This can be useful after a manual ROM image load with *MLOAD or *SRLOAD to quickly set the write protect before pressing BREAK.

Hardware overview

The module has a 256kb static RAM chip organised as 32k * 8 bit. This is the larger surface mount device on the boards. An ultra low power Atmel ATF22LV10CQZ programmable logic device (PLD) handles address decoding, chip select and write protect function.

The PLD has connections to the BBC synchronous write (NWDS) and the paged rom register selection (ROMSEL) signals via the jumper wires. It snoops on the data bus and captures any writes to the ROM selection register. This is used to determine which of the 4 banks should be mapped in at any given time and to control the write protect set/clear commands.

The PLD generates the chip select signals for the piggyback ROM and RAM chip. It also generates address line A14 for these chips to select between the upper and lower 16kB in the 32kB chips. Two single bit registers in the PLD are used to store the write protect status of the two 16kB RAM banks. The write signal NWDS is connected directly to the write enable pin on the RAM chip for timing purposes. If the bank's write protect is set then the PLD inhibits the chip select for the RAM during writes but allows reads as normal - thus making the RAM read only.

The board is jumperless (you don't need to configure it for which socket it is installed in) and the PLD determines the socket it is plugged into automatically on power up. This is done when the OS reads from the paged ROMs during initialisation. The PLD records the socket number it is plugged in to and uses this to work out if a set/clear RAM write protect command is for it or another board.